Computational Nanotechnology Research Group

Library of Relevant Publications

Research Needs for Novel Devices, May 2003 Edition. 2002 Novel Device Task Force, Nanostructure & Integration Sciences

Manipulation and Characterization of Molecular Scale Components. Amlani, I., Zhang, R., Tresek, J., Nagahara, L., Tsui, R.

Carbon nanotubes: nanomechanics, manipulation, and electronic devices. Avouris, Ph., Hertel, T., Martel, R., Schmidt, T., Shea, H.R., Walkup, R.E.

Logic Circuits with Carbon Nanotube Transistors. Bachtold, A., Hadley, P., Nakanishi, T., Dekker, C.

Logical Reversibility of Computation. Bennett, C.H.

The Thermodynamics of Computation -- a Review. Bennett, C.H.

The Future of Nanocomputing. Bourianoff, G.

The Future of Nanocomputing (presentation). Bourianoff, G.

Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips. Butts, M., DeHon, A., Goldstein, S.C.

Non-Crossing Ordered BDD for Physical Synthesis of Regular Circuit Structure. Cao, A. and Koh, C.

Electronically Configurable Molecular-Based Logic Gates. Collier, C. P., Wong, E. W., Belohradsky, M., Raymo, F. M., Stoddart, J. F., Kuekes, P. J., Williams, R. S., Heath, J. R.

Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown. Collins, P., Arnold, M., Avouris, Ph.

Nanotubes for Electronics. Collins, P., Avouris, Ph.

Small Wonders, Endless Frontiers: A Review of the National Nanotechnology Initiative. Committee for the Review of the National Nanotechnology Initiative

Catastrophic Faults in Reconfiguable Linear Arrays of Processors. De Prisco, R., De Santis, A.

Array-Based Architecture for FET-Based, Nanoscale Electronics. DeHon, A.

Nanowire-Based Sublithographic Programmable Logic Arrays. DeHon, A., Wilson, M.

Carbon Nanotube Inter- and Intramolecular Logic Gates. Derycke, V., Martel, R., Appenzeller, J. and Avouris, Ph.

C&EN exclusive Point-Counterpoint : Drexer - Smalley Debate. Drexler, K. E., Smalley, R.

Strategy and Prototype Tool for Doing Fault Modeling in a Nano-technology. Dysart, T., Kogge, P.

The Multiscalar Architecture. Franklin, M.

Bouncing Threads: Merging a new execution model into a nanotechnology memory. Frost, S., Rodrigues, A., Geifer, C., Kogge, P.

Memory in Motion: A Study of Storage Structures in QCA. Frost, S., Rodrigues, A., Janiszewski, A., Rausch, R., Kogge, P.

NanoFabrics: Spatial Computing Using Molecular Electronics. Goldstein, S. C., Budiu, M.

Fast Compilation for Pipelined Reconfigurable Fabrics. Goldstein, S. C., Budiu, M.

Digital Logic Using Molecular Electronics. Goldstein, S. C., Rosewater, D.

PipeRench: A Coprocessor for Streaming Multimedia Acceleration. Goldstein, S. C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R., Laufer, R.

Aspects of Systems and Circuits for Nanoelectronics. Goser, K., Pacha, C., Kanstein, A., Rossman, M.

A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. Heath, J., Kuekes, P., Snider, G., Williams, R. S.

Logic Gates and Computation from Assembled Nanowire Building Blocks. Huang, Y., Duan, X., Cui, Y., Lauhon, L., Kim, K., Lieber, C.

Directed Assembly of One-Dimensional Nanostructures into Functional Networks. Huang, Y., Duan, X., Wei, Q., Lieber, C.

Programming Systolic Arrays. Hughey, R.

Expanding Moore's Law: The Exponential Opportunity. Intel Corporation

Nanosys and Intel to Investigate Nanotechnology-Enabled Memory. Intel Corporation

Magnetoelectronic memories last and last…. Johnson, M.

Why the Future Doesn't Need Us. Joy, B.

FPGA Emulation of Quantum Circuits . Khalid, A., Zilic, Z., Radecka, K.

Cellular Gate Technology. Knight, T., Sussman, G.

Why Systolic Architectures. Kung, H. T.

Building Blocks of Biochemical CPU based on DNA Transcription Logic. Lauria, M., Bhalerao, K., Pugalanthiran, M., Yuan, B.

Mathematical Theory of Thermodynamics of Computation. Li, M., Vitanyi, P.

Mathematical Theory of Thermodynamics of Computation. Li, M., Vitanyi, P.

Molecular Memories That Survive Silicon Device Processing and Real-World Operation. Liu, Z., Yasseri, A., Lindsey, J., Bocian, D.

Compositional Reasoning Based on WEBRefinement for the Automatic Verification of Pipelined Machines. Manolios, P.

Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. Manolios, P., Srinivasan, S.

Computation in Cellular Automata: A Selected Review. Mitchell, M.

Design of Algorithmic Array Processors and its Applications. Peng, S.

Analogic CNN Computing : Architectural, Implementation, and Algorithmic Advances - a Review. Roska, T.

A Sticker Based Model for DNA Computation. Roweis, S., Winfree, E., Burgoyne, B.,Chelyapov, N., Goodman, M., Rothemund, P., Adleman, L.

Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing. Ruekes, T., Kim, K., Joselevich, E., Tseng, G., Cheung, C., Lieber, C.

Reconfigurability and Reliability of Systolic/Wavefront Arrays. Sha, E., Stieglitz, K.

General Parallel Computation without CPUs: VLSI Realization of a Particle Machine. Squier, R., Stieglitz, K., Jakubowski, M.

Molecular Electronics: From Devices and Interconnect to Circuits and Architecture. Stan, M., Franzon, P., Goldstein, S. C., Lach, J., Ziegler, M.

WaveScalar. Swanson, S., Michelson, K., Schwerin, A., Oskin, M.

Defects and Faults in Quantum Cellular Automata at Nano Scale. Tahoori, M., Momenzadeh, M., Huang, J., Lombardi, F.

Tutorial on Systolic Arrays. Tammemae, K.

The Future of Computing: The Next Big Thing?. The Economist

Toward Nanocomputers. Tseng, G., Ellenbogen, J.

Systematic Hardware Adaptation of Systolic Algorithms. Valero-Garcia, M., Navarro, J.

CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit. Ye, Z, A., Moshovos, A., Hauck, S., Banerjee, P.

Asymptotically Zero Energy Split-Level Charge Recovery Logic. Younis, S., Knight, T.

Nanoelectronic Scaling Tradeoffs: What does Physics have to say?. Zhirnov, V.

The CMOS/nano Interface from a Circuits Perspective. Ziegler, M., Stan, M.
NanoSys Report